Digital systems utilize timing signals to synchronize activity between circuit blocks. For example, as data signals pass from one circuit element to another or between circuits of a synchronous digital system, a clock signal is implemented to coordinate the actions of two or more elements of the circuits so that data signals may be accurately processed. A clock signal is typically a signal that oscillates between high and low voltage levels. Logic circuit elements respond to one or more features of the oscillating clock signal, such as a rising edge and/or a falling edge or some other function thereof. Clocking schemes can be based on other variations and other characteristics of a signal depending on the type of signal and the medium through which the signal traverses.
Systems may generate multiple clock signals based on a common system clock signal or a reference clock signal. For example, in one type of quadrature clocking system, timing circuits generate four clock signals that are ninety degrees out-of-phase with each other. Such quadrature clock signals can permit components of a system to increase performance relative to a reference clock signal. These signals can be distributed along multiple paths that permit a system to utilize parallel circuit components for distributing operations. The signal paths of each distributed clock signal throughout a circuit can be referred to as a clock tree.
Generally, as each clock signal advances along its branch of the clock tree, the signal may experience propagation delay. Propagation delays are affected by variables such as distance, temperature, supply voltage and process parameters. For example, at a low operating temperature with a high supply voltage, signals may be transmitted with a relatively short delay. It is not uncommon for different propagation delays to exist on different clock signal paths. This situation can cause the clock signals of the different clock paths to skew or shift out of phase with respect to their expected relationships with one another. This situation can cause a reduction in timing margins associated with data recognition windows for data signals. Thus, it would be beneficial to have a system that can maintain clock signal phase synchronization in the presence of different signal path propagation delays.